The present invention is related to the field of digital communications. More specifically, the present invention is directed to methods and/or systems and/or apparatuses for providing enhanced flow control in digital signals.
A number of prior art techniques have been proposed and developed for managing traffic in computer networks using flow control. Some references to known flow control implementations include:
1. ATM Generic Flow Control (GFC)xe2x80x94For UNI connections the first four bits of each ATM cell have been reserved for flow control. As in the present invention, the GFC were to communicate transmit-on/transmit-off (XON/XOFF) information, but unlike the present invention, this prior art flow control is applied to the entire link as opposed to a single virtual connection (VC).
2. BECN (Backward Explicit Congestion Notification)xe2x80x94This technique is per-VC flow control employed in ATM networks. The feedback is very slow ( less than 10 updates per second); therefore, large cell buffers must be used in conjunction to avoid cell loss.
3. ATM Forum Available Bit Rate (ABR) servicexe2x80x94Is based on specifying the ATM cell rate, as opposed to a simple XON/XOFF indication. ABR is more suited for end-to-end flow control within networks with large latencies. It lacks the simplicity of the present invention.
4. ATM Forum QFCxe2x80x94This is a credit based system. It lacks the simplicity of the present invention.
5. Transmission Control Protocol (TCP)xe2x80x94This is a Layer 4 end-to-end flow control (amongst other things) protocol.
6. T1 systemsxe2x80x94The timing is extracted from the raw frame rate of the link. This imposes the burden that the clock for link itself be very well controlled. With the present invention, a suitable line rate clock can generated with a simple 3rd overtone crystal oscillator that free runs.
7. SONET systemsxe2x80x94Again, synchronization is based on extracting timing from the frame rate.
8. SRTSxe2x80x94Synchronous Residual Time Stamp is a method for timing reference carriage across an ATM network. It generates a 4-bit remainder of the running phase difference between the source end clock and the network Stratum timing reference, transports this value to the receiving end, which then regenerates the source end clock from this 4-bit SRTS value and the Stratum reference.
The possibility of congestion is inherent in an access multiplexer, such as a DSLAM. In the downstream direction, the WAN link can generate a burst of cells for a particular modem at a rate exceeding the modem""s bandwidth capacity. Therefore, feedback to the traffic scheduler is required to cause it to buffer and smooth cell bursts to prevent downstream buffer overflow.
In the upstream direction, the aggregate bandwidth of all subscribers can exceed that accommodated by the WAN uplink. Flow control is generally required in a multiple access system to ensure fair access to the up-link, to minimize cell or data loss, and to minimize the impact of greedy users on others.
In DSLAM systems, such as described in greater detail in the references cited above, flow control has been adapted for a variety of prior architectures. One class of known prior DSLAM solutions uses packet or cell switch architectures. This requires signaling and traffic management functionality on the access port line cards and on the WAN uplink port card. Additionally, intercard switching is typically required in these solutions. Some examples of such solutions are Transwitch-Cubit-based switch architectures, Motorola-MPC860SAR-based architectures, and IgT-WAC-185/186/187/188-based switch architectures.
An alternative prior solution centralizes signaling and traffic management functionality on the WAN uplink port card by applying a shaping function on a port basis to all traffic in the downstream direction. This per port shaping function shapes the aggregate traffic to a port (such as an xDSL modem) to handling rate of that port. This solution thereby attempts to eliminate the need for further traffic management functionality on the access port line cards.
Various of these prior DSLAM flow control techniques suffer from a number of disadvantages, such as:
1. Significant increased complexity results from providing the signaling and traffic management functionality on both the access port line cards and the WAN uplink port card. This occurs due to the large number of access port line cards in a typical DSLAM, therefore requiring a large number of physical instances of this complex and costly functionality.
2. Placing the signaling and traffic management functionality on each access port and WAN uplink card additionally adds the requirement to provide intercard switching capability. The intercard switching solution is generally complex due to the large number of access port cards.
3. Placing the signaling and traffic management functionality on each access port and WAN uplink card additionally forces a distributed software control and provisioning requirement, thus adding significant complexity to the software layer.
4. Traffic latency and delay variation is increased due to the traffic transiting two traffic management structuresxe2x80x94one on the access port card and one on the WAN uplink card.
5. Solutions using per port traffic shaping to eliminate the need for traffic management functionality on the access line card, must adjust the shaping rate in real time, each time the access port changes rates. This will happen frequently when using rate adaptive splitterless xDSL technology.
6. Solutions using per port traffic shaping to eliminate the need for traffic management functionality on the access line card must ensure PHY buffer overflow is avoided. To do this, the shape rate must be less then the actual PHY rate, since the two rates are not synchronized. This rate difference represents a loss in throughput bandwidth.
The present invention is directed to providing improved flow control in certain digital communication environments. In various embodiments, the present invention may be embodied in devices, systems, and methods relating to digital communication.
In particular embodiments, the present invention may be most easily understood in the context of a Digital Subscriber Loop Access Multiplexer (DSLAM) architecture, such as the architecture described in the provisional applications referenced above. In particular embodiments, the present invention addresses issues that can arise in DSLAM architectures where the complexity of the system is concentrated in a few common cards, so that the multitude of line cards each are simple. In a particular example architecture, each XDSL signal has a relatively low bit rate and it is therefore technically feasible to perform ATM layer functions, such as traffic management, on a single entity. The invention, in particular embodiments, addresses a side-effect of removing traffic management queuing from individual line cards. This side effect is the need to pace the transfer of cells to the line card to avoid cell loss. The invention in specific embodiments uses a per-PHY flow-control mechanism to achieve this.
In specific aspects of specific embodiments, the invention provides a method of flow control in a digital communications system wherein data flows in one direction in a combined channel and in an opposite direction in multiple channels. In the combined channel, according to the invention, data units (such as cells or packets) have included in them a portion of data indicating available/not-available status of channels in the return direction. Before a channel in the return direction is selected for transmitting, the available/not-available status provided in the data portions is checked.
In further aspects, every data unit flowing in the combined channel contains such a portion. In a further aspect, each data unit only provides status of a subset of return channels and therefore multiple data units are needed to update the status of all return channels.
In a further aspect, there is a delay of one or more data units between the status provided in the portion and when the return scheduler receives the status portion and therefore sufficient buffering is provided one at the on said second channels to compensate for said delay.
In specific embodiments, portions can be encoded as a set of bit-flags, the state of each bit flag indicating available/not-available status of one of said channel in the return direction.
It will thus be seen that in specific embodiments, the invention provides a solution enabling real time PHY buffer status feedback. This eliminates the need for per port traffic shaping on an uplink card and further in various embodiments enables: (1) real time, automatic adjustment to PHY rate changes, thus avoiding PHY buffer overflow conditions which result in traffic loss and throughput inefficiency; (2) less complex traffic management functionality on the WAN uplink card due to removal of the per port traffic shaping function; and (3) maximization of the PHY bandwidth capability, since the port traffic is played out at the current maximum PHY rate. In various specific embodiments, the invention further: (1) is economically and technically scaleable; (2) has low latency to the feedback to avoid instabilities or need for extensive buffering; (3) has low bandwidth overhead for in-band and minimizes signal paths if out-of-band: and (4) uses flow control to avoid creating head-of-line blocking situations.
Other aspects of the present invention include a method for providing a timing reference over a data unit stream that allows frequency matching to any frequency less than the data unit transmission rate.
As used herein, cells should be understood to refer to ATM cells or to any other communications protocol data unit (such as packets or frames) that may be transmitted or scheduled as described by or understood from the teachings provided herein.
While the present invention is described herein in terms of a particular ATM system embodiment, using the teachings provided herein, it will be understood by those of skill in the art, that various methods and apparatus of the present invention may be advantageously used in other communication systems, including different ATM systems and systems based on different communications protocol, such as Ethernet, SONET, etc.
The invention will be better understood with reference to the following drawings and detailed descriptions. In different figures, similarly numbered items are intended to represent similar functions within the scope of the teachings provided herein.
Furthermore, it is well known in the art that logic systems can include a wide variety of different components and different functions in a modular fashion. Different embodiments of a system can include different mixtures of elements and functions and may group various functions as parts of various elements.
For purposes of clarity, the invention is described in terms of systems that include many different innovative components and innovative combinations of components. No inference should be taken to limit the invention to combinations containing all of the innovative components listed in any illustrative embodiment in this specification.
All publications, patents, and patent applications cited herein are hereby incorporated by reference in their entirety for all purposes.